DocumentCode
3474742
Title
350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node
Author
Morimoto, Takashi ; Harada, Yohmei ; Koide, Tetsushi ; Mattausch, Hans Jürgen
Author_Institution
Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan
fYear
2004
fDate
27-30 Jan. 2004
Firstpage
531
Lastpage
532
Abstract
We designed a cell-network-based full-custom test-chip for gray-scale/color image segmentation of real-time video-signals in 350nm CMOS technology. From this digital test-chip design, fully-integrated QVGA-size video-picture-segmentation chips, with 250μsec segmentation time per frame, at 10MHz are estimated to become possible at the 90nm technology node.
Keywords
CMOS integrated circuits; application specific integrated circuits; image segmentation; image sequences; real-time systems; video signal processing; 10 MHz; 350 nm; 90 nm; CMOS technology; CMOS test-chip; QVGA-size video-picture-segmentation chips; architecture verification; digital test-chip design; gray-scale/color image segmentation; real-time video-signals; CMOS technology; Clocks; Gray-scale; Image segmentation; Image storage; Pixel; Real time systems; Signal processing algorithms; Testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Print_ISBN
0-7803-8175-0
Type
conf
DOI
10.1109/ASPDAC.2004.1337634
Filename
1337634
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