A multi-mode power amplifier for enhanced PAE in back-off operation with load insensitive architecture

A novel multi-mode power amplifier (PA) concept with improved efficiency over a wide range of output power is presented. It incorporates three power back-off modes with enhanced efficiency and provides a high tolerance to load variations in all modes. This approach offers sufficient linearity for high crest factor signals such as WCDMA and EDGE without requiring any predistortion. The conditions for optimum operation of the PA topology, based on power combining of parallel amplifier stages with quadrature hybrids, are derived. The chip is implemented in a 0.35 mum SiGeC-bipolar technology. In GSM operation measurements at 840 MHz yield a peak power of 36.1 dBm at 52.5% PAE. In back-off WCDMA operation the PA yields, at an average max. power of 27 dBm, a PAE of 37% and at an average usecase power of 19 dBm a PAE of 27%. In EDGE operation at 29 dBm a PAE of 27% and a 3 dB margin to the system linearity specification are achieved.