Title :
A compact design of SEED block cipher
Author :
Pirpilidis, Filippos ; Kitsos, Paris ; Kakarountas, Athanasios
Author_Institution :
Comput. & Inf. Eng. Dept. (CIED), Technol. Educ. Inst. of Western Greece, Greece
Abstract :
An efficient compact implementation of the 128-bit SEED block cipher is presented in this paper. The proposed architecture achieves low level in hardware resources, so it is efficient for area constraints applications such as smart cards. The proposed implementation reaches a data throughput of 29.7 Mbps at 111 MHz clock frequency. The design was coded using VHDL language and for the hardware implementation, the Xilinx Artix 7 (xc7a100tl-csg324C) FPGA device was used.
Keywords :
cryptography; field programmable gate arrays; hardware description languages; SEED block cipher; VHDL language; Xilinx Artix 7 FPGA device; area constraints applications; data throughput; field programmable gate array; frequency 111 MHz; hardware resources; smart cards; very high speed description language; Ciphers; Clocks; Computer architecture; Field programmable gate arrays; Hardware; Registers; Throughput; FPGA implementation; SEED block cipher; compact implementation; cryptography;
Conference_Titel :
Embedded Computing (MECO), 2015 4th Mediterranean Conference on
Conference_Location :
Budva
Print_ISBN :
978-1-4799-8999-7
DOI :
10.1109/MECO.2015.7181881
