Standard cell library design with voltage scaling and transistor sizing for ultra-low-power biomedical applications

Author

Chio-In Ieong ; Mingzhong Li ; Man-Kay Law ; Pui-In Mak ; Mang-I Vai ; Peng-Un Mak ; Feng Wan ; Martins, Rui P.

Author_Institution

State Key Lab. of Analog & Mixed-Signal VLSI & FST/ECE, Univ. of Macau, Macau, China

fYear

2013

fDate

3-5 June 2013

Firstpage

1

Lastpage

2

Abstract

This paper reports the design and optimization of a standard cell library in 0.18μm CMOS, together with the analysis on voltage scaling and transistor sizing for ultra-low power biomedical applications. By simulating with a 8-bit 4-tap FIR filter at 0.6V clocked 100kHz, the design achieves 18.6× and 1.55× lower power consumption comparing to a commercial standard cell library working at nominal voltage 1.8V and re-characterized 0.6V.

Keywords

CMOS digital integrated circuits; FIR filters; MOSFET; biomedical electronics; cellular arrays; low-power electronics; CMOS; FIR filter; frequency 100 kHz; power consumption; size 0.18 mum; standard cell library design; transistor sizing; ultralow-power biomedical applications; voltage 0.6 V; voltage scaling; Capacitance; Inverters; Libraries; Logic gates; Power demand; Transistors; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of

Conference_Location

Hong Kong

Type

conf

DOI

10.1109/EDSSC.2013.6628062

Filename

6628062