Title :
A multi-band fully differential fractional-N PLL for wideband reconfigurable wireless communication
Author :
Xiaodong Liu ; Wenfeng Lou ; Liyuan Liu ; Nanjian Wu
Author_Institution :
State Key Lab. for Super lattices & Microstructures, Inst. of Semicond., Beijing, China
Abstract :
A fractional-N PLL for multi-standard transceiver is presented. The tuning range covers dual bands of 0.38~6 GHz and 9~12 GHz. A high-speed ultra-band divide-by-2 circuit is designed to accomplish the frequency band of 0.3 to 13.7 GHz. A novel high isolation multiplexer is presented to achieve the frequency band selection in LO paths. This chip was implemented with 65 nm CMOS technology and the maximum current consumption is 20.05 mA at 1.2 V power supply. The measured typical phase noise of the PLL is -114.6 dBc/Hz from 1 MHz offset for 4.85 GHz output and the reference spur and fractional spur are less than -48 dBc and -62.99 dBc respectively.
Keywords :
CMOS integrated circuits; low-power electronics; multiplexing equipment; phase locked loops; phase noise; radio transceivers; reference circuits; ultra wideband communication; CMOS technology; LO paths; current 20.05 mA; current consumption; fractional spur; frequency 0.3 GHz to 13.7 GHz; frequency band selection; high-speed ultraband divide-by-2 circuit; isolation multiplexer; multiband fully differential fractional-N PLL; multistandard transceiver; phase noise; reference spur; size 65 nm; voltage 1.2 V; wideband reconfigurable wireless communication; CMOS integrated circuits; Frequency division multiplexing; Frequency synthesizers; Phase locked loops; Phase noise; Wireless communication; PLL; multi-standard; multiplexer; phase noise;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of
Conference_Location :
Hong Kong
DOI :
10.1109/EDSSC.2013.6628067
