• DocumentCode
    347532
  • Title

    Reducing complexity of wafer flow to improve quality and throughput in a single-wafer cluster tool

  • Author

    Oh, Hilario L.

  • Author_Institution
    Silicon Valley Group Inc., San Jose, CA, USA
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    378
  • Lastpage
    388
  • Abstract
    A single-wafer cluster tool refers to a group of single-wafer process modules organized around a group of wafer transporters to perform a series of process steps on a wafer. To achieve high throughput, redundant modules and transporters are added to the cluster tool. The networking of the many redundant modules and transporters brings about complex wafer flow which requires complex coordination of wafer processing and transporting. Invariably, delays occur in transporting the wafer. If the delays occur at a gating module, the throughput slows down. If they occur in critical process modules, the on-wafer results are adversely affected. Furthermore, the process results will not be consistent because the wafers are not processed in similar flow paths. This paper presents a method for reducing the wafer flow complexity. By introducing “planned delays” to the process times of noncritical process modules, it is shown that (a) zero transport delays can be assured in gating modules and critical process modules; (b) periodicity can be introduced into the wafer flow. The consequence of (a) is an improvement in quality and throughput. The consequence of (b) is a drastic reduction in the number of possible wafer flow paths, thus ensuring consistent process results. A real life example of queueing to reduce the complexity in a photoresist processing system is presented to illustrate the concept and methodology
  • Keywords
    cluster tools; delays; integrated circuit manufacture; integrated circuit technology; manufacturing resources planning; materials handling; photoresists; quality control; cluster tool; complex wafer flow; critical process modules; delays; gating module; networking; photoresist processing system; planned delays; process consistency; process steps; process times; quality; queueing; redundant modules; redundant transporters; single-wafer cluster tool; single-wafer process modules; throughput; transport delays; wafer flow complexity; wafer flow paths; wafer flow periodicity; wafer processing; wafer transport; wafer transporters; Biographies; Delay; Design engineering; Fellows; Mechanical engineering; Robustness; Silicon; Technology management; Testing; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Manufacturing Technology Symposium, 1999. Twenty-Fourth IEEE/CPMT
  • Conference_Location
    Austin, TX
  • ISSN
    1089-8190
  • Print_ISBN
    0-7803-5502-4
  • Type

    conf

  • DOI
    10.1109/IEMT.1999.804849
  • Filename
    804849