DocumentCode
3475323
Title
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
Author
Weiping Shi ; Zhuo Li ; Alpert, C.J.
Author_Institution
Texas A&M University
fYear
2004
fDate
27-30 Jan. 2004
Firstpage
609
Lastpage
614
Abstract
As gate delays d e e m faster than wire delays for each teehnolagy generation, buffer insertion hecomes a popular method to reduce the interconnecI delay. Several modem huffer insertion algorithms (e.g.. 17.6.151) are based on van Ginneken??s dynamic programming paradigm [141. However, van Ginneken??s original algorithm does not control buffering resources and tends to over-buffering, thereby wasting area and power. It has been a major open prohlem whether it is possible to optimize slack and at the same time minimize the buffer usage. This paper settles this open problem by showing that for arbitrary integer cost functions, the problem is NP-complete. We also extend the prr-buffer slack technique (121 to minimize the buffer cost. This technique can significantly reduce the running time and memory in buffer cost miniminition problem. The experimental results show that our algorithm can speed up the running time up to 17 times and reduces the memory to 1/30 of traditional best know algorithm. Finally, we show how to efficiently deal with multiway merge in buffer insertion.
Keywords
Cost function; Delay; Dynamic programming; Explosions; Modems; Polynomials; Repeaters; Steiner trees; Timing; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Conference_Location
Yohohama, Japan
Print_ISBN
0-7803-8175-0
Type
conf
DOI
10.1109/ASPDAC.2004.1337664
Filename
1337664
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