DocumentCode
3475406
Title
Verification of timed circuits with symbolic delays
Author
Clariso, Robert ; Cortadella, J.
Author_Institution
Universitat Politecnica de Catalunya
fYear
2004
fDate
27-30 Jan. 2004
Firstpage
628
Lastpage
633
Abstract
Verifying timed circuits is a complex problem even when the delays of the system are fixed. This paper deals with a more challenging problem, the formal verification of timed circuits with unspecified delays represented as symbols. The approach discovers a set of sufficient linear constraints on the symbols that guarantee the correctness of the circuit. Experimental results from the area of asynchronous circuits show the applicability of the approach.
Keywords
Asynchronous circuits; Automatic testing; Clocks; Delay systems; Feedback; Flip-flops; Formal verification; Information analysis; Timing; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Conference_Location
Yohohama, Japan
Print_ISBN
0-7803-8175-0
Type
conf
DOI
10.1109/ASPDAC.2004.1337668
Filename
1337668
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