DocumentCode
3476072
Title
Realizable parasitic reduction for distributed interconnects using matrix pencil technique
Author
Wang, J. ; Saxena, P. ; Hafiz, O. ; Wang, X.
Author_Institution
University of Arizona
fYear
2004
fDate
27-30 Jan. 2004
Firstpage
781
Lastpage
786
Abstract
With the increasing design complexity, integrating realizable reduction techniques into design flows has shown more advantage than the traditional model order reduction methods. In this paper, we propose a realizable parasitic reduction method for RLGC distributed interconnects. The proposed method ohatains a reduced order model based on a modified matrix pencil method. By using a set of analytic formulas, this method provides synthesied RLGC elements. This new model is applied to power grid and antena circuits involving triangular input waveforms, lossy transmission lines and discontinuities of interconnects The results show better reduction ratio than the standard macromodels and good accuracy compared with the theoretical values.
Keywords
Circuit synthesis; Delay effects; Design automation; Frequency domain analysis; Integrated circuit interconnections; Power grids; Propagation losses; Reduced order systems; Time domain analysis; Transmission line matrix methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Conference_Location
Yohohama, Japan
Print_ISBN
0-7803-8175-0
Type
conf
DOI
10.1109/ASPDAC.2004.1337700
Filename
1337700
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