Flash Controller Design for FPGA Application

This paper designs a Flash controller, which helps the FPGA main state-machine to manage a Flash memory chip efficiently. The controller builds its own instruction set. User operates the proposed controller with the system clock of FPGA without caring about the timing sequences required by the Flash. The proposed Flash controller develops its own method for the reorganization and mapping of invalid blocks in a Flash chip. The design in this paper has been tested and verified with a customized FPGA board and proofed to be a promising candidate for the systems with Flash managed by FPGA directly.