Abstract :
While essential for high-performance circuit design, the custom nature of datapath components confines their use in only a few micropmessor companies. The reusability of datapath intellectual pmperty (IP) libraries is largely limited by their dependence on process technology. Layout migration tools today, which are based on layout compaction developed decades ago, cannot cope with the challenges involved. In this paper, we present B comprehensive datapath IP development framework that can perform process migration by accommodating advanced circuit considerations, layout architecture and transistor sizing, in addition to design mle satisfaction. We demonstrate the effectiveness of the framework by migrating the Berkeley low power library, originally developed for 1.2um MOSIS process, into TSMC 0.25μm and 0.18μm technology.
