Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor

We propose an integrated archltectural/physicdplanning approach named priority assignment optimization to mioimize the current surge in high performance power eifkient clock-gated microprocessors. The proposed approach balances the current demands across the floorplan by assigning optimized priorities to the functional unlts (FUs). Two complementary methods - physical planning with soft modules and h o e pattern management - to enhance our proposed approach are also dlscussed for various applications. Experimental results show that the proposed approach reduces the peak noise by 11.75% and consequently, the decoupllng capacitance (Decap) requirement by 24.22% without any degradation in IPC (Instruction Per Cycle). We also show that our approach does not Increase the clock period for the 0.18pm technology and beyond.