Design of test structures for electrical and reliability measurements in a 2.5D TSV interposer

Author

Huijuan Wang ; Jing Zhou ; Chongshen Song ; Daquan Yu ; Fengwei Dai ; Guidotti, Daniel ; Yang Song ; Pan Jie ; Qiu Delong ; He Huimin ; Wu Peng ; Tianmin Du ; Liqiang Cao ; Lixi Wan

Author_Institution

Inst. of Microelectron., Beijing, China

fYear

2013

fDate

11-14 Aug. 2013

Firstpage

41

Lastpage

45

Abstract

A 2.5D three-dimensional (3D) silicon interposer with through silicon vias (TSV) was designed and fabricated. All structures are for the purpose of evaluating the design and layout, electrical testing, and to evaluate process reliability of the 2.5D interposer. Three levels are tested: chip, interposer and plastic substrate. The paper details the layout of the three levels, the principal electrical tests and extraction of TSV parameters such as the resistance of TSVs pads and lines. The design structure also tests the reliability of the 2.5D package structure by thermal stressing. The electrical test results are discussed in relation to applicability at high frequencies.

Keywords

elemental semiconductors; integrated circuit layout; integrated circuit manufacture; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; silicon; thermal stresses; three-dimensional integrated circuits; 2.5D TSV interposer; 2.5D package structure; Si; electrical measurements; electrical testing; electrical tests; reliability measurements; test structures design; thermal stressing; three-dimensional silicon interposer; through silicon vias; Coplanar waveguides; Layout; Reliability; Resistance; Silicon; Substrates; Through-silicon vias; 2.5D interposer; Design for test; Through Silicon Vias (TSV);

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Packaging Technology (ICEPT), 2013 14th International Conference on

Conference_Location

Dalian

Type

conf

DOI

10.1109/ICEPT.2013.6756417

Filename

6756417