High-level area and power-up current estimation considering rich cell library

Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces large power-up current that may affect circuit reliability as well as introduce performance loss. We present an in-depth study of high-level power-up current modeling and estimation in the context of a full custom design environment with a rich cell library. We propose a methodology to estimate the circuit area in terms of gate count and maximum power-up current for any given logic function. We build novel estimation metrics based on logic synthesis and gate level analysis using only a small number of typical circuits, but no further logic synthesis and gate level analysis are needed during our estimation. Compared to time-consuming logic synthesis and gate level analysis, the average errors for circuits from a leading industrial design project are 23.59% for area and 21.44% for maximum power-up current. In contrast, estimation based on quick synthesis leads to llx area difference in gate count for an Bbit adder.