Relating linearity test results to design flaws of pipelined analog to digital converters

This paper is an analysis of linearity errors inherent in pipelined analog to digital converter (ADC) architectures. We explain the architecture, demonstrate the error mechanisms affecting linearity test results, and compare the behavioral DC model linearity data to actual test data. Design and process shortcomings are illustrated in a “cause and effect” fashion. The goal is to help “design debug” by relating the ATE generated integral nonlinearity plots to actual design flaws of the converter