Investigation of silicon stress around through silicon vias by high efficiency micro-Raman microscopy

Through silicon vias (TSVs) attract considerable amount of attention and activity in recent years as a main means to achieve three-dimensional (3D) integrated circuit (IC) functionality. However, the new technology poses new integration challenges as well as new reliability challenges. This paper presents the latest progress in TSV non-destructive stress testing by means of micro-Raman microscopy, a technique which is approved to be the method of choice for identifying stress on silicon surface. The principle of micro-Raman microscopy for TSV measurement is illustrated. By using commercially available micro-Raman microscopy tools, silicon stress around vias having a diameter of 30 μm and a depth of 160 μm has been visualized under optimized conditions.