A new type of wafer level package based on silicon substrate

WLCSP (wafer level chip scale package) has been well accepted within modern industry which brings not only the reduction of package size, but also good thermal performance vs. more traditional peripherally leaded packages. At the mean time, WLCSP feathers can significantly lower manufacturing costs. One of the barriers for WLCSP package to be accepted in the industry is the lack of existing and mature SMT and PCB technology with more and more tightened pitches of solder balls. Therefore, demands for cost-efficient packages come out when ball pitch is tightened less than 0.4mm. A new package way named Si-BGA is introduced in this paper. This package related process such as RDL and bumping, chip to wafer, flip-chip bonding, and capillary underfill is introduced. The structure of the prototype is characterized and the die level reliability is tested. The Si-BGA package demonstrated good reliability and can be used in low-k products.