Optimal Pipeline Depth and Supply Voltage for Power-constrained Processors

The overall system cost and other considerations require that processors deliver high performance within a given power budget. Pipelining and supply voltage, both affect the performance and power consumption. Therefore, pipelining depth can be varied simultaneously with appropriate adjustments in supply voltage so as to keep power consumption constant while affecting performance of a processor. This paper describes a novel methodology to explore optimum combination of pipeline depth and supply voltage to maximize performance while keeping power consumption constant. The ideal pipeline depth is shown to increase with higher power budget. Under variable supply voltage, the peak performance is only moderately sensitive to pipeline depth. Also it has been empirically observed that design with low-threshold devices delivers higher performance at the same power budget at the same pipeline depth than high-threshold devices, when operated at appropriate supply voltage.