A programmable 8.3mW, 0.5–100MHz BW, 88.3–48.1dB SNDR VCO-based ADC with switched capacitor linearization

Author

El-Halwagy, Waleed ; Dessouky, Mohamed ; El-Ghitani, Hassan

Author_Institution

Ain Shams Univ. (ASU), Cairo, Egypt

fYear

2013

fDate

3-5 June 2013

Firstpage

1

Lastpage

2

Abstract

A low power linearized 9-bit VCO-based ADC is presented. The proposed ADC employs a differential VCO coupling technique to enhance the VCO time resolution and a linearization switched capacitor feedback loop for improving the SNDR of the ADC. The proposed 200MHz ADC implemented in 130nm CMOS process showed an SNR/SNDR ranging from 91.4/88.3dB to 54.3/41.2dB for an input bandwidth of 500kHz - 100MHz while consuming a total of 8.3mW from a 1.2V supply.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; circuit feedback; linearisation techniques; low-power electronics; programmable circuits; switched capacitor networks; voltage-controlled oscillators; CMOS process; SNDR improvement; SNR; VCO time resolution enhancement; analog-to-digital converter; bandwidth 0.5 MHz to 100 MHz; differential VCO coupling technique; input bandwidth; linearization switched capacitor feedback loop; low power linearized 9-bit VCO-based ADC; noise figure 88.3 dB to 48.1 dB; power 8.3 mW; programmable VCO-based ADC; size 130 nm; voltage-controlled oscillator; word length 9 bit; Signal to noise ratio; Voltage-controlled oscillator(VCO); analog-to-digital converter(ADC); coupled VCO; switched capacitor feedback;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of

Conference_Location

Hong Kong

Type

conf

DOI

10.1109/EDSSC.2013.6628161

Filename

6628161