A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays

Design methodologies such as Razor minimize power dissipation by slowing down circuits so as to eliminate timing slacks to the point where occasional timing errors are observed. The main challenge here is the design of efficient mechanisms to detect and recover from these infrequent errors without loss of functionality. We present a design for widely used Wallace multipliers where, because of the highly skewed input based statistical distribution in completion delays, the potential for power and performance gains is significantly higher. Clock periods can be potentially reduced by a factor of 2 or more, with very rare timing errors for random input distributions. For error recovery we present a novel approach that latches and holds logic values at key internal circuit nodes during every clock cycle beyond the next clock edge. This allows generation of the correct outputs for that clock period one clock cycle later in case of a timing error. Meanwhile, very fast error evaluation, exploiting a unique characteristic of carry ripple addition, allows this hold to be quickly released if an error is not detected, ensuring no impact on the circuit timing in error free operation. Our approach is shown to deliver comparable performance to the fastest multipliers at substantially reduced power and hardware costs.