Input Referred Offset Reduction in Very High Speed Differential Receivers

This paper explains a circuit architecture to minimize the impact of IRO (Input Referred Offset) in Differential amplifier based Receivers. Such receivers are used on high speed interfaces, like DDRs and LVDS, as they provide better timing and ensure proper detection of small swing signals. However the mismatch between the differential input arms causes IRO which in turn causes duty cycle distortion and degrades the receiver timing. At very high speeds it becomes necessary to minimize the impact of IRO. The proposed IRO reduction circuit uses a Digital controller which measures and reduces the IRO using a binary code. The timing improvement provided by this circuit scheme is validated on Silicon in 28nm CMOS process.