Failure analysis of output stage due to ESD stress in submicron CMOS technology

Author

Huang Xiaozong ; Shi Jiangang ; Huang Wengang ; Liu Fan

Author_Institution

Analog IC Design Center, Sichuan Inst. of Solid-state Circuits, Chongqing, China

fYear

2013

fDate

3-5 June 2013

Firstpage

1

Lastpage

2

Abstract

ESD failure of an operational amplifier in submicron CMOS technology is analyzed to locate the failure mechanism and re-design the protection structure in this paper. From the experimental results, the specifications related to the output stage with large size devices are degraded or exceed the qualified range. With the deep analysis of internal circuit of the chip, electrical measurement determines the failure mechanism. The protection of power rail is not robust enough for shunting the ESD current under ND and PS modes. RC+BigFET clamp is used to improve the ESD robustness of whole chip to 3500V which is qualified for most applications.

Keywords

CMOS integrated circuits; electric variables measurement; electrostatic discharge; failure analysis; integrated circuit design; network analysis; operational amplifiers; ESD current; ESD failure; ESD robustness; ESD stress; ND modes; PS modes; RC-BigFET clamp; deep internal circuit analysis; electrical measurement; failure analysis; failure mechanism; operational amplifier; protection structure redesign; submicron CMOS technology; voltage 3500 V; CMOS integrated circuits; CMOS technology; Current measurement; Robustness; failure analysis; output stage; power rail protection;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of

Conference_Location

Hong Kong

Type

conf

DOI

10.1109/EDSSC.2013.6628165

Filename

6628165