Title :
Low-voltage miller divide-by-three circuit integrated with a 1.5-GHz QVCO
Author :
Huang, Chen-Wei ; Chang, Shih-Hsin ; Tsai, Pei-Kang ; Huang, Tzuen-Hsi
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan
Abstract :
In this work, the integration design of a low-voltage quadrature Miller divide-by-3 circuit are proposed and targeted for the UWB RF frequency synthesizer use. Some novel circuit schematics have been proposed and designed for the low-voltage operation. The chip was fabricated by a 0.18 mum RF-CMOS technology. The function of divide-by-3 has been successfully demonstrated together with the integration of a 1.5-GHz QVCO. Due to the parasitic capacitance loading, the measured output frequency finally has shifted to 448 MHz. The measured power consumption is about 34.8 mW drawn from the 1.2 V power supply.
Keywords :
CMOS integrated circuits; UHF integrated circuits; frequency dividers; frequency synthesizers; mixed analogue-digital integrated circuits; mixers (circuits); radiocommunication; voltage-controlled oscillators; Miller divide-by-three circuit; QVCO; RF-CMOS technology; UWB RF frequency synthesizer; frequency 1.5 GHz; power 34.8 mW; quadrature Miller circuit; size 0.18 mum; voltage 1.2 V; Capacitance measurement; Energy consumption; Frequency measurement; Frequency synthesizers; Integrated circuit measurements; Parasitic capacitance; Power measurement; Power supplies; Radio frequency; Semiconductor device measurement;
Conference_Titel :
Microwave Conference, 2008. APMC 2008. Asia-Pacific
Conference_Location :
Macau
Print_ISBN :
978-1-4244-2641-6
Electronic_ISBN :
978-1-4244-2642-3
DOI :
10.1109/APMC.2008.4957870
