A MIMD rendering algorithm for distributed memory architectures

Author

Crockett, Thomas W. ; Orloff, Tobias

Author_Institution

NASA Langley Res. Center, Hampton, VA, USA

fYear

1993

fDate

25-26 Oct 1993

Firstpage

35

Abstract

We present a parallel rendering algorithm targeted to MIMD distributed-memory message-passing architectures. For maximum performance, the algorithm exploits both object-level and image level parallelism. The behavior of the algorithm is examined both analytically and experimentally. The results show that the choice of message size has a significant impact on performance. Scalability to large numbers of processors is found to be limited primarily by communication overheads. An experimental implementation for the Intel iPSC/860 confirms the analytical results and demonstrates increasing performance from 1 to 128 processors across a wide range of scene complexities

Keywords

rendering (computer graphics); Intel iPSC/860; MIMD distributed-memory message-passing architectures; MIMD rendering algorithm; communication overheads; distributed memory architectures; image level parallelism; object level parallelism; scene complexities; Algorithm design and analysis; Computer architecture; Graphics; Layout; Memory architecture; NASA; Parallel processing; Performance analysis; Pipelines; Rendering (computer graphics);

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Rendering Symposium, 1993

Conference_Location

San Jose, CA

Print_ISBN

0-8186-4920-8

Type

conf

DOI

10.1109/PRS.1993.586083

Filename

586083