DocumentCode
3477426
Title
Multiphase Technique to Speed-up Delay Measurement via Sub-sampling
Author
Vasudevamurthy, Rajath ; Amrutur, Bharadwaj
Author_Institution
Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
fYear
2013
fDate
5-10 Jan. 2013
Firstpage
185
Lastpage
190
Abstract
A multi-phase technique for speeding up the measurement of delays via sub-sampling is presented. Measurement of delays using the sub-sampling approach leads to a very simple system implementation, and also provides the opportunity of trading off between bandwidth and accuracy. Such a scheme becomes extremely attractive for deep sub-micron processes due to its highly-digital nature and the ability to offer compact, low power, mixed-signal implementation alternatives. However, a drawback is the amount of averaging (measurement time) that is needed to get accurate results. A multiphase input clock scheme is proposed to address this issue, especially for the measurement of small delays, thereby speeding up the overall measurement. Simulation results from MATLAB Simulink confirm the speedup achieved upto a factor of eight with an eight-phase clock input for sufficiently small fixed test delays and also an improvement in SNR upto 11dB for slowly varying test delays.
Keywords
CMOS integrated circuits; VLSI; clocks; delays; integrated circuit measurement; integrated circuit testing; sampling methods; Matlab-Simulink; SNR; VLSI circuits; deep submicron processes; deep-sub-micron CMOS processes; delay measurement; multiphase input clock scheme; multiphase technique; small fixed test delays; subsampling approach; Accuracy; Clocks; Delay; Inverters; Phase measurement; Radiation detectors; Deep sub-micron; Sub-sampling; mixed-signal;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 2013 26th International Conference on
Conference_Location
Pune
ISSN
1063-9667
Print_ISBN
978-1-4673-4639-9
Type
conf
DOI
10.1109/VLSID.2013.186
Filename
6472637
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