• DocumentCode
    3477473
  • Title

    Design of sub-100nm SOI CMOS for RF switch application

  • Author

    Sajjadi, Ali ; Woo, J.C.S.

  • Author_Institution
    Dept. of Electr. Eng., UCLA, Los Angeles, CA, USA
  • fYear
    2013
  • fDate
    3-5 June 2013
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    Device design considerations and trade-offs of sub-100nm SOI CMOS for RF switch application are discussed. A new device structure, which improves 1-dB compression point (P1dB) of the switch by more than 6dB, is proposed. Experimental data will be presented.
  • Keywords
    CMOS integrated circuits; microwave switches; radiofrequency integrated circuits; silicon-on-insulator; RF switch application; SOl CMOS; Si; compression point; device design; size 100 nm; Feeds; Radio frequency; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of
  • Conference_Location
    Hong Kong
  • Type

    conf

  • DOI
    10.1109/EDSSC.2013.6628178
  • Filename
    6628178
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3477473