Design and Implementation of a High-Speed, Power-Efficient, Modified Hybrid-Mode Sense Amplifier for SRAM Applications

In this paper, a modified hybrid-mode sense amplifier (SA) for low power SRAM applications is being proposed using CMOS 180 nm technology. In order to overcome the observed limitations of the conventional hybrid-mode SA in terms of the sensing delay, the data line (DL) split has been made faster by partially blocking the bit line (BL) discharge in the proposed topology. The modified SA circuit has recorded 18.61% and 12.74% less sensing delays in the schematic and post layout level respectively. It has also shown a 9.64% improvement in terms of average power consumption. The design achieved much improved robustness with the variation of different design parameters, such as load capacitance, supply voltage, BL and DL capacitances.