Low power quadrature-input programmable frequency divider

Quadrature-phase clock signals are essential for in-phase and quadrature-phase (IQ) mixing in direct-conversion wireless transceiver systems. One way to generate such signals is to use quadrature VCO (QVCO). Many techniques have been reported to improve the IQ phase mismatch of the QVCO. However, in practical application, the imbalance of the QVCO output loading, which is normally due to the input capacitance of the frequency divider, will seriously deteriorate the IQ phase matching. In most of the frequency divider architectures, only differential input signals are needed. In order to balance the QVCO output loading, a dummy divider is usually connected to the remaining pair of QVCO outputs. The dummy divider is also advised to be turned on so that it will provide identical loading condition as that of the main divider. In this way, the capacitive loading between the QVCO outputs can be properly balanced. Its major drawback is the increased chip area and power consumption due to the dummy divider. In this work, a new quadrature-input programmable frequency divider design is proposed and fabricated in a 0.35 mum standard CMOS process. The novel quadrature-input divide-by-8 injection-locked frequency divider (ILFD) offers several advantages, such as reduced power consumption, providing balance capacitive loading for QVCO, and generating unique 45deg- spaced phase sequence for subsequent phase-switching. Together with backward-phase- selection scheme, the glitch problem is solved without power-hungry synchronizing circuit.