The process and stress-induced variability issues of trigate CMOS devices

Not only the popular random dopant fluctuation (RDF), but also the traps, caused by the hot carrier stress induce the V_th variations. This paper will address the importance of these effects and the experimental demonstration of the process- and trap-induced fluctuations. The boron clustering, sidewall roughness, and the electrical stress effects can all be justified by the theory and the method. This method provides us a valuable tool for the understanding of the process and stress induced variability in 3D devices (e.g., FinFET).