DocumentCode
3477642
Title
Power-Aware Wrappers for Transaction-Level Virtual Prototypes: A Black Box Based Approach
Author
Mbarek, Ons ; Pegatoquet, Alain ; Auguin, Michel ; Fathallah, H.E.
Author_Institution
LEAT, Univ. of Nice Sophia Antipolis, Sophia Antipolis, France
fYear
2013
fDate
5-10 Jan. 2013
Firstpage
239
Lastpage
244
Abstract
Low power design and verification at the Electronic System Level (ESL) have recently emerged as a challenging research field. This work presents a reliable solution to add such capabilities to Transaction-Level virtual prototypes composed of black-box hardware Intellectual Properties (IPs). This solution relies on a wrapper-based approach in which power intent specification and verification are added as separate layers of the IPs functional ones. Using Synopsys´s InnovatorTM virtual prototyping toolset, our approach has been validated with an audio application TL platform. Results show our approach benefits to enable different power intent alternatives exploration with low simulation speed overhead and reduced modeling effort.
Keywords
electronics industry; industrial property; low-power electronics; virtual prototyping; Synopsys Innovator virtual prototyping toolset; black-box hardware intellectual properties; electronic system level; power intent specification; power intent verification; power-aware wrappers; transaction-level virtual prototypes; Contracts; IP networks; Phasor measurement units; Prototypes; Registers; Standards; Virtual prototyping; Design-by-Contract (DbC); Intellectual Properties (IPs); Power Domain (PD); System-on-Chip (SoC); Transaction Level Models (TLM); Unified Power Format (UPF) standard; low power design and verification; power intent; virtual prototyping (VP);
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 2013 26th International Conference on
Conference_Location
Pune
ISSN
1063-9667
Print_ISBN
978-1-4673-4639-9
Type
conf
DOI
10.1109/VLSID.2013.194
Filename
6472646
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