Epi avoidance for CMOS logic devices using MeV implantation

Using MeV ion implantation and Cz bulk wafer denuding/gettering techniques, we have successfully demonstrated in bulk (non-epi) wafers superior latch-up performance and equivalent surface silicon quality (gate oxide integrity and junction leakage current) to that of p/p+ epi wafers resulting in direct retrofit replacement of epi wafers in manufacturing. Latch-up device characteristics will be presented comparing epi, retrograde wells, buried layers and BILLI (Buried Implanted Layer for Lateral Isolation) structures, Up to a 30× reduction in lateral current gain (B₁) was measured resulting in a 5× increase in n+ trigger current at <2.0 um n+ to p+ spacing. Also, optimizing various pre-process and/or process induced denuding and gettering have resulted in epi quality bulk Cz wafer surfaces. For a CMOS Logic manufacturing point of view, up to 16% reduction in total process cycle time/complexity can be realized equating to a cost savings of >$229 per 200 mm wafer. This paper summarizes the various MeV epi replacement alternatives describing the advantages and limitations of each from a production implementation point of view