Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages

Testing of a system-on-chip (SoC) consists of a schedule of test sessions. In each session, a subset of cores of the SoC is tested such that the peak power consumption of each core as well as that of the entire SoC remain under specified limits. In this work, we assume that each test session can be assigned its own clock frequency and V_DD, which are related through the critical path delay constraint and together determine the power consumption. Integer linear programming (ILP) is used to find optimal test schedules with lower test time than was possible before. We show that the test time of ASIC Z, for which the best previously published time is 300 time units, is reduced to 155 units by optimally selecting the clock frequency and V_DD for each session.