Physics Based Fault Models for Testing High-Voltage LDMOS

This paper presents a fault model based test technique for high-voltage laterally-diffused metal oxide semiconductor field effect transistor (HV-LDMOS) to test for structural defects such as gate-FOX breakdown, gate-stress due to thermal overload and drain leakage due to high voltage stress. We have developed highly accurate equivalent circuit models for HV-LDMOS which is represented as a hybrid model and has been validated for different device geometries including both large and small gate-channels. The hybrid model is incorporated to develop fault models for testing and diagnosis of HV-LDMOS. We have developed fault models for structural defects by inducing their physical effect in the HV-LDMOS hybrid model. HV-LDMOS testing is performed by connecting the device in common-emitter configuration and computing its gain by using a chopped test stimulus and capturing the device response using a digitizer. The test measurements are further processed using a lock-in amplifier (noise-reduction scheme) in MATLAB-Simulink software platform. The proposed test technique is low-cost and highly accurate.