DocumentCode
3477888
Title
VAST: Post-Silicon VAlidation and Diagnosis of RF/Mixed-Signal Circuits Using Signature Tests
Author
Deyati, Sabyasachi ; Banerjee, Adrish ; Muldrey, Barry John ; Chatterjee, Avhishek
Author_Institution
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear
2013
fDate
5-10 Jan. 2013
Firstpage
314
Lastpage
319
Abstract
Post-silicon validation of RF/mixed-signal circuits is challenging due to the need to excite all possible operational modes of the DUT in order to establish equivalence between its specified and observed behaviors and to ensure that the DUT does not produce any unexpected behaviors that can lead to system failure. In this research, we first develop a methodology for determining if the DUT contains behaviors that are not explicitly included in its behavioral model. A complex (optimized) test waveform is applied to the DUT and its test response signature is captured. It is seen that in the presence of unexpected DUT behaviors, the residual error in the test response signature from that defined by the model, cannot be minimized below a certain threshold by manipulating the model parameters in any way. If however, it is determined that the model is adequate but the signature is different from the expected, then a procedure is developed for determining which sub module is responsible for the difference (i.e. causes the system level specifications to be different from that specified by the behavioral model). Experiments on an RF transceiver are performed to demonstrate the effectiveness of the proposed validation and diagnosis approach.
Keywords
integrated circuit testing; mixed analogue-digital integrated circuits; DUT; RF transceiver; RF/mixed-signal circuits; VAST; behavioral model; post-silicon validation; signature tests; system failure; test response signature; Computational modeling; Mathematical model; Mixers; Radio frequency; Receivers; Transceivers; Transmitters; OFDM transceiver; Post silicon validation; fault detection; fault diagnosis; fault location; reliability; verification;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 2013 26th International Conference on
Conference_Location
Pune
ISSN
1063-9667
Print_ISBN
978-1-4673-4639-9
Type
conf
DOI
10.1109/VLSID.2013.207
Filename
6472659
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