• DocumentCode
    3477891
  • Title

    Compact models of emerging devices

  • Author

    Chi-Shuen Lee ; Yu Shimeng ; Ximeng Guan ; Jieying Luo ; Lan Wei ; Wong, H.-S Philip

  • Author_Institution
    Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
  • fYear
    2013
  • fDate
    3-5 June 2013
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    Compact modeling of resistive switching memory (RRAM) and carbon nanotube field-effect transistor (CNFET) are presented. The models are suitable for exploration of device design space, assessment of device performance at the circuit level. Optimization of the CNFET device structure to minimize the gate delay is presented as a demonstration of the model´s capability. Simulation of neuromorphic computation system is an example application of the RRAM model. The models can be used to perform advance explorations of circuits and sub-systems of emerging devices prior to the availability of reliable, high-yielding fabrication processes for the emerging devices.
  • Keywords
    carbon nanotube field effect transistors; random-access storage; semiconductor device models; C; CNFET device structure; RRAM; carbon nanotube field-effect transistor; compact models; device design space; device performance; gate delay; neuromorphic computation system; optimization; resistive switching memory; CNTFETs; Computational modeling; Integrated circuit modeling; Logic gates; Performance evaluation; Resistance; Tunneling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of
  • Conference_Location
    Hong Kong
  • Type

    conf

  • DOI
    10.1109/EDSSC.2013.6628197
  • Filename
    6628197