A 10-bit low-power differential successive approximation ADC for implantable biomedical application

Energy efficient analog-to-digital converters (ADCs) are needed to accommodate implantable biomedical application. This paper presents a high energy efficiency successive approximation ADC with fully differential architecture. In order to improve the energy efficiency, the circuit works at 1-V supply voltage and adopts the self-timed logic to ease the power consumption of the comparator. Simulation results show that the proposed circuit designed with a 0.18-μm CMOS technology can achieve a sampling rate of 100 kS/s, effective number of bit of 9.87 and power consumption of 6.7 μW, which leading to a Figure of Merit as low as 71 fJ/conv-level.