K-Algorithm: An Improved Booth´s Recoding for Optimal Fault-Tolerant Reversible Multiplier

Fault-tolerant multipliers with low power consumption are the need of today´s computing systems and reversible circuits have emerged as an efficient solution for ultra-low power design. In this paper, we propose an improved Booth´s recoding algorithm named as K-Algorithm for signed multiplication which reduces the hardware complexity. An efficient multiplier architecture for implementation of K-Algorithm is also proposed. Based on Booth´s recoding algorithm, we design 4-bit reversible multipliers, with and without fault-tolerance. We also design a fault-tolerant reversible multiplier using K-Algorithm. We analyze all the three proposed designs using the reversible logic design metrics: quantum cost, number of ancilla bits, number of garbage outputs, and number of gates. We then compare our reversible multiplier designs with the existing designs reported in literature and find that on an average, our K-Algorithm based fault-tolerant design reduces the quantum cost by 33% and other design metrics are also considerably reduced. Overall, the proposed fault-tolerant reversible multiplier based on K-Algorithm is most optimal as compared to all other designs.