Title :
MVL circuit design and characterization at the transistor level using SUS-LOC
Author :
Kinvi-Boh, E. ; Aline, M. ; Sentieys, O. ; Olson, Edgar D.
Author_Institution :
ENSSAT, Univ. of Rennes, Lannion, France
Abstract :
This paper deals with design and performance estimation of typical ternary functions using SUS-LOC concepts. Experimental models of the transistors needed for SUS-LOC structures are presented. A created characterization process allows to extract the delay and the energy consumption information from each cell which is simulated at the transistor level. Finally, VHDL is used to obtain performances modelling and architectural-level simulation. Some characterization results are presented for basic logic ternary functions and a comparison between binary and ternary circuits is given for two adder structures.
Keywords :
adders; hardware description languages; logic design; multivalued logic; multivalued logic circuits; transistors; MVL circuit design; SUS-LOC concept; VHDL; adder structure; architectural-level simulation; binary circuit; energy consumption information; experimental transistor model; ternary circuit; transistor level; typical ternary function; Adders; CMOS logic circuits; CMOS technology; Circuit synthesis; Energy consumption; Integrated circuit technology; Logic circuits; Logic devices; Very large scale integration; Voltage;
Conference_Titel :
Multiple-Valued Logic, 2003. Proceedings. 33rd International Symposium on
Print_ISBN :
0-7695-1918-0
DOI :
10.1109/ISMVL.2003.1201392
