RTL modeling of the RCMP egress routing logic

We present our results on the RTL modeling and simulation of an egress traffic module, using both VHDL and Verilog. The design considered is a commercial product obtained from PMC-Sierra Inc. and is used by the RCMP (routing, cell counting, monitoring, policing) process in a network port interface for an ATM switch fabric. The egress routing logic of RCMP does header translation of ATM cells and aids multicasting. The behavioral specification of the egress routing logic was realized in an RTL VHDL and Verilog implementation. The work also involved the simulation of the RTL VHDL and Verilog models using Synopsys-VSS and Verilog-XL tools respectively. Improper synchronization between the processes leading the system to an indefinite "pause" state was discovered by simulation and later rectified.