Title :
A low-power, 9-Bit, 1.2 ps resolution two-step time-to-digital converter in 65 nm CMOS
Author :
Hamza, A. ; Ibrahim, S. ; El-Nozahi, M. ; Dessouky, M.
Author_Institution :
Electron. & Commun. Eng. Dept., Ain Shams Univ., Cairo, Egypt
Abstract :
This paper presents the design of a low-power, 9-bit, two-step time-to-digital converter (TDC) in 65 nm CMOS. Instead of using an array of time amplifiers (TAs) to amplify the time residue, the proposed TDC reduces the power and area consumptions by using only one TA. The designed TDC achieves a resolution of 1.2 ps with a conversion range of 0.614 ns while consuming 0.602 mW at 10 MHz and 8.299 mW at 150 MHz. The achieved figure-of-merit (FoM) of the TDC is 0.108 pJ/conversion at a frequency of 150 MHz.
Keywords :
CMOS integrated circuits; time-digital conversion; CMOS; figure-of-merit; frequency 10 MHz; frequency 150 MHz; low-power time-to-digital converter; power 0.602 mW; power 8.299 mW; size 65 nm; time 1.2 ps; two-step time-to-digital converter; Arrays; CMOS integrated circuits; Calibration; Delays; Detectors; Flip-flops; Logic gates; Time-to-digital converter (TDC); all-digital phase-locked loop (ADPLL); time amplifier (TA);
Conference_Titel :
New Circuits and Systems Conference (NEWCAS), 2015 IEEE 13th International
Conference_Location :
Grenoble
DOI :
10.1109/NEWCAS.2015.7182045
