Title :
A field-programmable digital filter chip using multiple-valued current-mode logic
Author :
Degawa, Katsuhiko ; Aoki, Takafumi ; Higuchi, Tatsuo
Author_Institution :
Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
Abstract :
This paper presents a Field-Programmable Digital Filter (FPDF) IC that employs carry-propagation-free redundant arithmetic algorithms for faster computation and multiple-valued current-mode circuit technology for high-density low-power implementation. The prototype FPDF fabrication with 0.6 μm CMOS technology demonstrates that the chip area and power consumption can be reduced to 41% and 74%, respectively, compared with the standard binary logic implementation.
Keywords :
CMOS logic circuits; digital filters; digital signal processing chips; field programmable gate arrays; multivalued logic circuits; redundant number systems; CMOS technology; FPDF; carry-propagation-free redundant arithmetic algorithms; chip area; field-programmable digital filter chip; multiple-valued current-mode logic circuit technology; power consumption; standard binary logic implementation; Digital filters; Logic;
Conference_Titel :
Multiple-Valued Logic, 2003. Proceedings. 33rd International Symposium on
Print_ISBN :
0-7695-1918-0
DOI :
10.1109/ISMVL.2003.1201408
