Experimental and simulation studies of single-electron-transistor-based multiple-valued logic

Periodic drain current-gate voltage characteristics of single-electron transistors (SETs) were utilized to construct basic components of multiple-valued logic (MVL), such as a universal literal gate and a quantizer. In order to supplement the small gain and the small applicable voltage of the SET, hybrid SET-MOSFET scheme is proposed and demonstrated experimentally using CMOS-compatible pattern-dependent oxidation (PADOX) technology. We also succeeded in reproducing the results using a SPICE circuit simulator with a compact analytical SET model, and estimated the performance of the proposed MVL.