Dynamic combined pattern-parallel and fault-parallel fault simulation on computational RAM

Computational RAM (C/spl middot/RAM) is a logic-enhanced memory architecture that supports massively-parallel bit-serial computation. Previous work (J.A. Waicukauski et al., 1987; B.F. Cockburn et al., 1998, A.L.-C. Kwong, 1998) investigated the implementation of fault-parallel and pattern-parallel fault simulation algorithms on C/spl middot/RAM. The fault-parallel strategy was found to be efficient at the start of the simulation but inefficient at the end. The converse behaviour was observed for the pattern-parallel strategy. A dynamic hybrid algorithm combines the fault-parallel and pattern-parallel strategies in an adjustable proportion so as to obtain the best aspects of both. This paper describes a dynamic hybrid fault simulator for C/spl middot/RAM that models the detection in combinational logic of stuck-at faults, transition faults of order 1, and CMOS transistor stuck-open faults.