DocumentCode :
34787
Title :
A 6.5-Gb/s 1-mW/Gb/s/CH Simple Capacitive Crosstalk Compensator in a 130-nm Process
Author :
Kyu-Dong Hwang ; Lee-Sup Kim
Author_Institution :
Sch. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Volume :
60
Issue :
6
fYear :
2013
fDate :
Jun-13
Firstpage :
302
Lastpage :
306
Abstract :
A capacitive crosstalk compensator (CXC) at a transmitter is presented. It employs double-path capacitive coupling to cancel accurately crosstalk-induced jitter. A mode detector and an additional clock for compensation are eliminated, and only buffers and capacitors are used. The simple architecture consumes low power (1 mW/Gb/s/CH) and occupies small area (0.009 mm2/CH). The chip was fabricated in a 130-nm CMOS process. CXC has the maximum jitter reduction of 34.1 ps (90.5%) and the maximum voltage improvement of 26.6 mV. CXC operates at up to 6.5 Gb/s.
Keywords :
CMOS integrated circuits; capacitors; clocks; compensation; coupled circuits; crosstalk; detector circuits; jitter; transmitters; CMOS process; CXC; bit rate 6.5 Gbit/s; buffer; capacitor; clock; crosstalk-induced jitter; double-path capacitive coupling; maximum jitter reduction; maximum voltage improvement; mode detector; simple capacitive crosstalk compensator; size 130 nm; time 34.1 ps; transmitter; voltage 26.6 mV; Capacitive coupling; crosstalk; crosstalk-induced jitter (CIJ); far-end crosstalk (FEXT);
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2013.2258252
Filename :
6507609
Link To Document :
بازگشت