Signal-power integrity co-simulations of high speed systems via chip-package-PCB co-analysis methodology

Under the platform of a high-speed package system, a modeling method considering all the significant effects from the chip, package, and board levels is developed to identify and investigate the critical nets affecting the signal or power integrity(SI/PI). For SI issues, accurate modelings for signal channel are verified by system of high speed line. The following what-if analyses help to identify the package trace´s bottlenecks and have great effects on signal transmission. For PI part, the modeling methodologies for power distribution networks of data line are demonstrated and validated with the results of frequency domain simulation. Lastly, with the co-simulations by chip-package-PCB model, the paper was talked about the SI and PI problem using SI-PI co-analysis methodology. The analysis results indicates that the parasitic effects of the high speed package system are the most critical, depicting the importance of improved package design in the next high speed package system.