Integration of a 200 V, 60 MHz lateral PNP transistor with emitter-base self-aligned to polysilicon into a high voltage BiCMOS process

A 200-V BV_CEO (breakdown voltage) lateral PNP transistor with improved frequency response over conventional designs has been designed and fabricated, utilizing only the existing layers of a BiCMOS process suitable for power integrated circuits. The self-alignment of the emitter and base implants to the edge of a polysilicon field plate provides a narrow, graded base region with a very repeatable base width. The 2.5 μm base width provides a f _τ (unity-gain frequency) value that is 40 times larger than that of conventional lateral PNPs with the same BV_CEO . During layout the extended collector length is drawn only as long as is necessary to achieve the required breakdown voltage, resulting in a significant area savings, minimal collector resistance, and reduced power dissipation