Temperature-dependant thermal stress analysis of through-silicon-vias during manufacturing process

Thermal stress is induced by high temperature manufacturing processes, due to the mismatch of Coefficient of Thermal Expansion s (CTE) between silicon, dielectric material and copper. In this paper, thermal stress around Through-Silicon-Vias (TSVs) was discussed using 3D FEA transient method. Stress distributions near a TSV and TSVs array were investigated after dielectric liner deposition, barrier layer deposition and annealing process, respectively. Moreover, stress distribution around a via was impacted by the thickness of the dielectric liner, the via diameter, the via pitch and the cooling speed during annealing process. In order to verify the simulation results, TSV samples were fabricated through a series of processes. Si Raman shift profiles near a TSV was also measured and calculated. The simulation results coincided with the real measurement value in tolerable error range.