Parallel Deadlock Detection and Recovery for Networks-on-Chip Dedicated to Diffused Computations

Parallelized kernels for operations research belong to the class of the diffused computations of Dijkstra and Scholten. They communicate through small, constant-length (or at least bounded length) messages and quickly reach congestion. FPGAs allow the creation of many-cores architectures and, because they are reconfigurable, can embed networks-on-a-chip (NoCs) that have been finely tuned for these kernel\´s specificities. This article concerns the first step towards the future design of routing strategies: the proposal of a deadlock detection and recovery algorithm. This "non deadlock-freeness" has two motivations: be NoC\´s topology and routing strategies independent to allow for total freedom in the design of routing strategies. A formal proof of the algorithm is then given. Synthesis confirms its O(N.(L+2.log(N))) area complexity order. Simulation of a 3600 cores SoC using an underlying 30x30 simplex mesh (not full duplex, then not deadlock free) validates these contributions. A graph representing the Rome city in Italy, that contains 3353 vertexes and 8870 arcs, has been successfully tested.