Digital Late-Transition Metastability Simulation Model

As modern systems-on-chip contain increasingly more clock domain crossings, the associated metastability effects become much more pronounced. To maintain the reliability of the design, efficient means for metastability analysis become mandatory. We propose an approach that allows simulation of late transitions, the most dominant effect of metastability in modern VLSI chips. While this approach is purely digital and hence very fast, it allows a precise treatment in the time domain. These properties make it attractive for modeling even complex circuit structures. The core of our approach is a timing model that carefully maps the relative times of setting the latch opaque and the arrival of new data at the input to the appropriate data-input/output delay. Unlike with existing models this mapping is not simply linear and hence restricted to a very narrow scope, it rather works for arbitrary inter-arrival times between data and enable. We systematically elaborate an analytic description of this input/output delay and illustrate how the respective model parameters can be derived from an initial circuit simulation, either automatically or with manual support. Once calibrated, the model allows fast and precise simulation, which we illustrate in a case study.