Title :
Process Examination of Through Silicon Via Technologies
Author_Institution :
Nagano Prefectural Inst. of Technol., Nagano
fDate :
Jan. 16 2007-Yearly 18 2007
Abstract :
Several processes for obtaining through silicon via (TSV) electrodes in active integrated circuit chips are classified and examined. The classification is made as seven different categories according to their forming process and final configurations. They are compared each other from the viewpoint of process freedom, metal contamination, circuit versatility, electrical characteristics, possible production yield and cost forecast.
Keywords :
active networks; contamination; electrodes; integrated circuit interconnections; integrated circuit yield; TSV electrodes; active integrated circuit chips; circuit versatility; forming process; metal contamination; process examination; process freedom; production yield; through silicon via electrodes; Contamination; Costs; Electric variables; Electrodes; Integrated circuit technology; Integrated circuit yield; Load forecasting; Production; Silicon; Through-silicon vias; Through silicon via; bump; electrodes; interconnection;
Conference_Titel :
Polymers and Adhesives in Microelectronics and Photonics, 2007. Polytronic 2007. 6th International Conference on
Conference_Location :
Odaiba, Tokyo
Print_ISBN :
978-1-4244-1186-3
Electronic_ISBN :
978-1-4244-1186-3
DOI :
10.1109/POLYTR.2007.4339157
